[en] Ultralow substrate crosstalk is demonstrated using a novel metal Faraday cage isolation scheme in silicon-on-insulator technology. Over ten times reduction in crosstalk is demonstrated up to 10 GHz, compared to previously reported substrate crosstalk suppression technologies.
Disciplines :
Electrical & electronics engineering
Author, co-author :
Stefanou, Stefanos
Hamel, John Stan
Baine, Paul
Bain, M.
Armstrong, B. Mervyn
Gamble, Harold S.
Kraft, Michaël ; Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes microélectroniques intégrés
Kemhadjian, H. A.
Language :
English
Title :
Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology
Publication date :
2004
Journal title :
IEEE Transactions on Electron Devices
ISSN :
0018-9383
Publisher :
Institute of Electrical and Electronics Engineers, United States
K. Joardar, "A simple approach to modeling crosstalk in integrated circuits," IEEE J. Solid-State Circuits, vol. 29, pp. 1212-1219, Oct. 1994.
K. To, P. Welch, S. Bharatan, H. Lehning, T. Huynh, R. Thoma, D. Monk, W. Huang, and V. Ilderem, "Comprehensive study of substrate noise isolation for mixed-signal circuits," in IEDM Tech. Dig., Dec. 2001, pp. 519-522.
J. Raskin, A. Viviani, D. Flandre, and J. Colinge, "Substrate crosstalk reduction using SOI technology," IEEE Trans. Electron Devices, vol. 44, pp. 2252-2261, Dec. 1997.
J. Hamel, S. Stefanou, M. Bain, B. Armstrong, and H. Gamble, "Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes (GPSOI)," IEEE Microwave Guided Waves Lett., vol. 10, pp. 134-135, Apr. 2000.
N. Pham, K. Ng, M. Bartek, P. Sarro, B. Rejaei, and J. Burghartz, "A micromaching post-process module for RF silicon technology," in IEDM Tech. Dig., 2002, pp. 481-484.
J. Wu, J. Scholvin, J. del Alamo, and K. Jenkins, "A Faraday cage isolation structure for crosstalk suppression," IEEE Microwave Wireless Comp. Lett., vol. 11, pp. 410-412, Oct. 2001.
H.-S. Kim, K. Jenkins, and Y.-H. Xie, "Effective crosstalk isolation through p+ Si subtrates with semi-insulation porous Si," IEEE Electron Device Lett., vol. 23, pp. 160-162, Mar. 2002.
N. Zamdmer, A. Ray, J. Plouchart, L. Wagner, N. Fong, K. Jerkins, W. Jin, and P. Smey, "A 0.13 μm SOI CMOS technology for low-power digital and RF application," in VLSI Tech. Dig., 2001.
W. Goh, J. Montgomery, S. Raza, B. Armstrong, and H. Gamble, "The manufacture and performance of diodes made in dielectrically isolated silicon substrates containing buried metallic layers," IEEE Electron Device Lett., vol. 20, pp. 212-214, May 1999.
S. Stefanou, J. Hamel, M. Bain, B. Armstrong, H. Gamble, R. Mauntel, and M. Huang, "Physics and compact modeling of SOI substrates with buried ground plane (GPSOI) for substrate noise suppression," in IEEE Int. Microwave Symp. Dig., May 2001, pp. 1877-1880.
C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RF ics," IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, May 1998.