Operating the power electronics of a superconducting system at low temperatures: mitigation of interface trap effects in a p-type MOS capacitor

In this study, the electrical response of metal-oxide-semiconductor (MOS) capacitors is studied at both room and cryogenic temperatures, emphasizing the impact of interface traps on the capacitance-voltage (C-V) characteristics. The capacitors are obtained by depositing SiO_2 layers by means of radio-frequency magnetron sputtering over a (100) p-type Si substrate. Electrical measurements performed between 293 K and 50 K reveal pronounced non-ideal effects that are more significant at low temperatures, they include hysteresis, frequency dispersion of the capacitance in the accumulation regime, and the appearance of a ledge in the depletion region. In addition, a memory effect is observed, demonstrating that the low-temperature electrical behavior of the MOS capacitor depends on its thermal and electrical history. Observations show that the application of a fixed bias voltage during the cooling process can significantly modify the flat-band voltage and, under specific conditions, reduce interface-trap-related effects such as hysteresis and depletion ledge. This work provides a framework for improving the electrical stability and the C-V response of MOS capacitor in low-temperature power applications.