Mitigation of Interface Trap-Induced Bump Effects in p-Type MOS Capacitor

The behavior of a SiOx/p-type Si MOS capacitor is explored under cryogenic conditions highlighting the impact of interface traps on its C-V characteristics. The work provides a framework for improving MOS capacitor functionality in low-temperature power applications. At cryogenic temperatures, a bump effect emerges in the depletion region, linked to slow electron capture/emission dynamics of traps. The study reveals a memory effect tied to prior thermal and voltage history, alongside hysteresis and capacitance dispersion in the accumulation region. By applying voltage during the cooling process, the flat-band voltage can be manipulated, providing a strategy to reduce the bump effect and improve performance.