Abstract :
[en] We have developed a straightforward die-level thinning process suitable for Silicon-On-Insulator (SOI) dies. The process has been demonstrated on SOI CMOS die assembled on rigid and flexible PCBs using previously-developed anisotropic conductive adhesive flip-chip method. Unlike standard wafer-level thinning processes, in the demonstrated process the full thickness SOI die is directly mounted on PCB and after that thinned. The demonstrated process is simple and robust; it comprises fewer process steps compared to conventional die thinning process. The ultra-thinning process has no effects on the assembly integrity and device performance.
Funders :
The work was supported by the Microsystème_ULg Microsys project, funded by the Wallonia (Belgium), and the Micro+ project cofounded by the European Regional Development Fund (ERDF) and Wallonia (Belgium).
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