Multistage Linear Feedback Shift Register Counters with Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications

Morrison, D.; Delic, D.; Yuce, M. R.; Redouté, Jean-Michel

doi:10.1109/TVLSI.2018.2872021

Article (Scientific journals)

Multistage Linear Feedback Shift Register Counters with Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications

Morrison, D.; Delic, D.; Yuce, M. R. et al.

2019 • In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27 (1), p. 103-115

Peer Reviewed verified by ORBi

Permalink
https://hdl.handle.net/2268/239236

DOI
10.1109/TVLSI.2018.2872021

Files (1)Send to Details Statistics Bibliography Similar publications

Files

Full Text

2019 - Multistage Linear Feedback Shift Register Counters.pdf

Publisher postprint (3.27 MB)

Request a copy

All documents in ORBi are protected by a user license.

Send to

RIS BibTex APA Chicago Permalink X Linkedin

Details

Keywords :

CMOS integrated circuits; Computer circuits; Decoding; Feedback; Frequency converters; Particle beams; System-on-chip; Binary counters; Large-scale arrays; Linear feedback shift registers; Proof of concept; Single photon detection; System on chip design; Time to digital converters; Shift registers

Abstract :

[en] Linear-feedback shift register (LFSR) counters have been shown to be well suited to applications requiring large arrays of counters and can improve the area and performance compared with conventional binary counters. However, significant logic is required to decode the count order into binary, causing system-on-chip designs to be unfeasible. This paper presents a counter design based on multiple LFSR stages that retains the advantages of a single-stage LFSR but only requires decoding logic that scales logarithmically with the number of stages rather than exponentially with the number of bits as required by other methods. A four-stage four-bit LFSR proof of concept was fabricated in 130-nm CMOS and was characterized in a time-to-digital converter application at 800 MHz. © 1993-2012 IEEE.

Disciplines :

Electrical & electronics engineering

Author, co-author :

Morrison, D.; Department of Electrical and Computer Systems Engineering, Monash University, Clayton, VIC 3800, Australia

Delic, D.; Defence Science and Technology Group, Edinburgh, SA 5111, Australia

Yuce, M. R.; Department of Electrical and Computer Systems Engineering, Monash University, Clayton, VIC 3800, Australia

Redouté, Jean-Michel ; Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes microélectroniques intégrés

Language :

English

Title :

Multistage Linear Feedback Shift Register Counters with Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications

Publication date :

2019

Journal title :

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

ISSN :

1063-8210

Publisher :

Institute of Electrical and Electronics Engineers Inc.

Volume :

Issue :

Pages :

103-115

Peer reviewed :

Peer Reviewed verified by ORBi

Available on ORBi :

since 06 September 2019

Statistics

Number of views

107 (1 by ULiège)

Number of downloads

0 (0 by ULiège)

More statistics

Scopus citations^®

Scopus citations^®
without self-citations

OpenCitations

OpenAlex citations

Bibliography

D. Bronzi, Y. Zou, F. Villa, S. Tisa, A. Tosi, and F. Zappa, "Automotive three-dimensional vision through a single-photon counting SPAD camera," IEEE Trans. Intell. Transp. Syst., vol. 17, no. 3, pp. 782-795, Mar. 2016.
I. Vornicu, R. Carmona-Galán, and A. Rodríguez-Vázquez, "A CMOS 0.18 ?m 64×64 single photon image sensor with in-pixel 11 b timeto-digital converter," in Proc. Int. Semiconductor Conf. (CAS), 2014, pp. 131-134.
M. Perenzoni, D. Perenzoni, and D. Stoppa, "A 64×64-pixels digital silicon photomultiplier direct TOF sensor with 100-MPhotons/s/pixel background rejection and imaging/altimeter mode with 0.14% precision up to 6 km for spacecraft navigation and landing," IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 151-160, Jan. 2017.
J. M. Pavia, M. Scandini, S. Lindner, M. Wolf, and E. Charbon, "A 1×400 backside-illuminated SPAD sensor with 49.7 ps resolution, 30 pJ/sample TDCs fabricated in 3D CMOS technology for near-infrared optical tomography," IEEE J. Solid-State Circuits, vol. 50, no. 10, pp. 2406-2418, Oct. 2015.
C. Niclass, M. Soga, H. Matsubara, M. Ogawa, and M. Kagami, "A 0.18-?m CMOS SoC for a 100-m-range 10-frame/s 200×96-pixel time-of-flight depth sensor," IEEE J. Solid-State Circuits, vol. 49, no. 1, pp. 315-330, Jan. 2014.
R. Ballabriga, M. Campbell, E. Heijne, X. Llopart, L. Tlustos, and W. Wong, "Medipix3: A 64 k pixel detector readout chip working in single photon counting mode with improved spectrometric performance," Nucl. Instrum. Methods Phys. Res. A, Accel. Spectrom. Detect. Assoc. Equip., vol. 633, pp. S15-S18, May 2011.
J. Kim, S. Park, M. Hegazy, and S. Lee, "Comparison of a photoncounting-detector and a CMOS flat-panel-detector for a micro-CT," in Proc. IEEE Nucl. Sci. Symp. Med. Imag. Conf. (NSS/MIC), 2013, pp. 1-4.
F. Villa et al., "SPAD smart pixel for time-of-flight and time-correlated single-photon counting measurements," IEEE Photon. J., vol. 4, no. 3, pp. 795-804, Jun. 2012.
H. Mo and M. P. Kennedy, "Masked dithering of MASH digital deltasigma modulators with constant inputs using multiple linear feedback shift registers," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 6, pp. 1390-1399, Jun. 2017.
K. J. Sham, S. Bommalingaiahnapallya, M. R. Ahmadi, and R. Harjani, "A 3×5-Gb/s multilane low-power 0.18-?m CMOS pseudorandom bit sequence generator," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 5, pp. 432-436, May 2008.
A. Ajane, P. M. Furth, E. E. Johnson, and R. L. Subramanyam, "Comparison of binary and LFSR counters and efficient LFSR decoding algorithm," in Proc. IEEE 54th Int. Midwest Symp. Circuits Syst. (MWSCAS), Aug. 2011, pp. 1-4.
S. Soh et al., "16 bit multi-energy level detecting photon counting ROIC," in Proc. IEEE Nucl. Sci. Symp. Med. Imag. Conf. Rec. (NSS/MIC), Oct./Nov. 2012, pp. 801-804.
M. K?osowski, W. Jendernalik, J. Jakusz, G. Blakiewicz, and S. Szczepanski, "A CMOS pixel with embedded ADC, digital CDS and gain correction capability for massively parallel imaging array," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 64, no. 1, pp. 38-49, Jan. 2017.
D. Bronzi et al., "100 000 frames/s 64×32 single-photon detector array for 2-D imaging and 3-D ranging," IEEE J. Sel. Topics Quantum Electron., vol. 20, no. 6, pp. 354-363, Nov. 2014.
D. W. Clark and L.-J. Weng, "Maximal and near-maximal shift register sequences: Efficient event counters and easy discrete logarithms," IEEE Trans. Comput., vol. 43, no. 5, pp. 560-568, May 1994.
N. Mukherjee, A. Pogiel, J. Rajski, and J. Tyszer, "High-speed on-chip event counters for embedded systems," in Proc. 22nd Int. Conf. VLSI Design, 2009, pp. 275-280.
T. A. Abbas, N. A. W. Dutton, O. Almer, N. Finlayson, F. M. D. Rocca, and R. Henderson, "A CMOS SPAD sensor with a multievent folded flash time-to-digital converter for ultra-fast optical transient capture," IEEE Sensors J., vol. 18, no. 8, pp. 3163-3173, Apr. 2018.
M.-A. Tetrault, E. D. Lamy, A. Boisvert, R. Fontaine, and J.-F. Pratte, "Low dead time digital SPAD readout architecture for realtime small animal PET," in Proc. IEEE Nucl. Sci. Symp. Med. Imag. Conf. (NSS/MIC), Oct. 2013, pp. 1-6.
N. Krstajic et al., "A 256 × 8 SPAD line sensor for time resolved fluorescence and raman sensing," in Proc. 40th Eur. Solid-State Circuits Conf. (ESSCIRC), 2014, pp. 143-146.
N. Mukherjee, J. Rajski, G. Mrugalski, A. Pogiel, and J. Tyszer, "Ring generator: An ultimate linear feedback shift register," IEEE Comput., vol. 44, no. 6, pp. 64-71, Jun. 2011.
D. Bronzi, F. Villa, S. Tisa, A. Tosi, and F. Zappa, "SPAD figures of merit for photon-counting, photon-timing, and imaging applications: A review," IEEE Sensors J., vol. 16, no. 1, pp. 3-12, Jan. 2016.
V. Friedman and S. Liu, "Dynamic logic CMOS circuits," IEEE J. Solid-State Circuits, vol. JSSC-19, no. 2, pp. 263-266, Apr. 1984.
P. Alfke, "Efficient shift registers, LFSR counters, and long pseudorandom sequence generators," Xilinx Inc., San Jose, CA, USA, Tech. Rep. XAPP 052, Jul. 1996.
R. Cunha, H. Boudinov, and L. Carro, "Quaternary look-up tables using voltage-mode CMOS logic design," in Proc. 37th Int. Symp. Multiple-Valued Logic (ISMVL), 2007, p. 56.
C. Yoo, "A CMOS buffer without short-circuit power consumption," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 9, pp. 935-937, Sep. 2000.
L. Ding and P. Mazumder, "On circuit techniques to improve noise immunity of CMOS dynamic logic," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 9, pp. 910-925, Sep. 2004.
M. Alioto, G. Palumbo, and M. Pennisi, "Understanding the effect of process variations on the delay of static and domino logic," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 5, pp. 697-710, May 2010.
K. Martin, "Digital integrated system building blocks," in Digital Integrated Circuit Design. New York, NY, USA: Oxford Univ. Press, 2000, pp. 407-408.