Verduijn, J., Tettamanzi, G.C., Rogge, S., Wave function control over a single donor atom (2013) Nano Letters, 13 (4), pp. 1476-1480
Deshpande, V., Wacquez, R., Vinet, M., Jehl, X., Barraud, S., Coquand, R., Roche, B., Faynot, O., 300 K operating full-CMOS integrated single electron transistor (SET)-FET circuits (2012) International IEEE Electron Devices Meeting, pp. 871-874. , December
Klymenko, M.V., Remacle, F., Quantum dot ternary-valued full-Adder: Logic synthesis by a multiobjective design optimization based on a genetic algorithm (2014) Journal of Applied Physics, 116 (16), p. 164316
Seo, M., Hong, C., Lee, S.-Y., Choi, H.K., Kim, N., Chung, Y., Umansky, V., Mahalu, D., Multi-valued logic gates based on ballistic transport in quantum point contacts (2014) Scientific Reports, 4
Remacle, F., Heath, J.R., Levine, R.D., Electrical addressing of confined quantum systems for quasiclassical computation and finite state logic machines (2005) Proceedings of the National Academy of Sciences of the United States of America, 102 (16), pp. 5653-5658
Byeon, D., Lee, S., Lim, Y., Park, J., Han, W., Kwak, P., Kim, D., Suh, K., An 8 Gb multi-level NAND ash memory with 63 nm STI CMOS process technology (2005) Proceedings of the IEEE International Solid-State Circuits Conference, 1, pp. 46-47. , February
Wong, H.-S.P., Raoux, S., Kim, S., Liang, J., Reifenberg, J.P., Rajendran, B., Asheghi, M., Goodson, K.E., (2010) Phase Change Memory. Proceedings of the IEEE, 98 (12), pp. 2201-2227. , December
Han, J., Orshansky, M., Approximate computing: An emerging paradigm for energy-efficient design (2013) Proceedings of the IEEE European Test Symposium, pp. 1-6. , May
Sampson, A., Nelson, J., Strauss, K., Ceze, L., Approximate storage in solid-state memories (2013) Proceedings of the ACM/ IEEE Annual International Symposium on Microarchitecture, pp. 25-36. , December
Inokawa, H., Fujiwara, A., Takahashi, Y., A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors (2003) IEEE Transactions on Electron Devices, 50 (2), pp. 462-470
Klein, M., Lansbergen, G.P., Mol, J.A., Rogge, S., Levine, R.D., Remacle, F., Reconfigurable logic devices on a single dopant atom-operation up to a full adder by using electrical spectroscopy (2009) ChemPhysChem, 10 (1), pp. 162-173
Lavieville, R., Triozon, F., Barraud, S., Corna, A., Jehl, X., Sanquer, M., Li, J., Niquet, Y., Quantum dot made in metal oxide silicon-nanowire field effect transistor working at room temperature (2015) Nano Letters
Pekola, J.P., Vartiainen, J.J., Mottonen, M., Saira, O., Meschke, M., Averin, D.V., Hybrid single-electron transistor as a source of quantized electric current (2008) Nature Physics, 4 (2), pp. 120-124
Nishiguchi, K., Ono, Y., Fujiwara, A., Operation of silicon single-electron devices at room temperature (2007) NTT Technical Reviews Letters, 5 (6), pp. 1-6
Seo, M., Hong, C., Lee, S.-Y., Choi, H.K., Kim, N., Chung, Y., Umansky, V., Mahalu, D., Multi-valued logic gates based on ballistic transport in quantum point contacts (2014) Scientific Reports, , 4, January
Kogge, P.M., Stone, H.S., A parallel algorithm for the efficient solution of a general class of recurrence equations (1973) IEEE Transactions on Computers, 100 (8), pp. 786-793
Sjalander, M., Nilsson, N.S., Kaxiras, S., A tunable cache for approximate computing (2014) Proceedings of the IEEE International Symposium on Nanoscale Architecture, pp. 88-89. , July
Inokawa, H., Fujiwara, A., Takahashi, Y., A multiple-valued SRAM with combined single-electron and MOS transistors (2001) Proceedings of the Device Research Conference, pp. 129-130. , June
Esmaeilzadeh, H., Sampson, A., Ceze, L., Burger, D., Architecture support for disciplined approximate programming (2012) Proceedings of the Architectural Support for Programming Languages and Operating Systems, pp. 301-312
Mohapatra, D., Chippa, V.K., Raghunathan, A., Roy, K., Design of voltage-scalable meta-functions for approximate computing (2011) Proceedings of the Conference on Design, Automation and Test in Europe, pp. 1-6. , IEEE
Kahng, A.B., Kang, S., Kumar, R., Sartori, J., Slack redistribution for graceful degradation under voltage overscaling (2010) Proceedings of the Asia and South Pacific Design Automation Conference, pp. 825-831. , IEEE
Sampson, A., Dietl, W., Fortuna, E., Gnanapragasam, D., Ceze, L., Grossman, D., EnerJ: Approximate data types for safe and general low-power computation (2011) Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 164-174. , June
Mielke, N., Marquart, T., Wu, N., Kessenich, J., Belgal, H., Schares, E., Trivedi, F., Nevill, L.R., Bit error rate in NAND ash memories (2008) Proceedings of the IEEE International Reliability Physics Symposium, pp. 9-19. , IEEE
Muralimanohar, N., Balasubramonian, R., Jouppi, N.P., (2009) CACTI 6.0: A Tool to Model Large Caches. Technical Report HPL-2009-85, , HP Laboratories April
Ielmini, D., Lacaita, A.L., Mantegazza, D., Recovery and drift dynamics of resistance and threshold voltages in phase-change memories (2007) IEEE Transactions on Electron Devices, 54 (2), pp. 308-315
Yeo, S., Seong, N.H., Lee, H.-H.S., Can multi-level cell PCM be reliable and usable? Analyzing the impact of resistance drift (2012) Proceedings of the Workshop on Duplicating, Deconstructing and Debunking, , June
Cai, Y., Haratsch, E.F., Mutlu, O., Mai, K., Error patterns in MLC NAND ash memory: Measurement, characterization, and analysis (2012) Proceedings of the Conference on Design, Automation and Test in Europe, pp. 521-526. , IEEE