EMI susceptibility of high speed differential wireline communication front-ends

Computer circuits; Magnetic susceptibility; Transmitters; Comparative analysis; Current mode logic; Differential logic; Differential signalling; Electromagnetic susceptibilities; Low voltage differential signaling; Signal Integrity; Wire-line communications; Electromagnetic compatibility

Abstract :

[en] This paper presents an in-depth electromagnetic susceptibility (EMS) analysis for three commonly used differential high speed wireline interfaces, namely: low voltage differential signaling (LVDS), current mode logic (CML) and voltage mode logic (VML). The behavior of each differential transmitter structure is explained in detail on how its operation is being affected when subjected to a worst case EMI injection. A comparative analysis shows how the CML transmitter structure is more robust to EMI than its voltage mode counterparts. Simulation results are presented to demonstrate how EMI corrupts the transmitters' signal integrities despite the differential signalling scheme. These results illustrate that EMI can corrupt each structure by completely closing the differential logic magnitude starting from a 175mV differential amplitude when EMI is not present. Furthermore, both LVDS and VML are affected by EMI at a frequency range spanning from 30MHz to 300MHz while CML is affected from 300MHz to 1.5GHz. These transmitters were designed and simulated using UMC 180nm process. © 2016 IEEE.

Disciplines :

Electrical & electronics engineering

Author, co-author :

Matig-A, G.; Biomedical Circuits and Sensors Laboratory, Dept. of Electrical and Computer Systems Engineering, Monash University, Melbourne, Australia

Yuce, M. R.; Biomedical Circuits and Sensors Laboratory, Dept. of Electrical and Computer Systems Engineering, Monash University, Melbourne, Australia

Redouté, Jean-Michel ; Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes microélectroniques intégrés

Language :

English

Title :

EMI susceptibility of high speed differential wireline communication front-ends

Publication date :

2016

Event name :

2016 International Symposium on Electromagnetic Compatibility, EMC EUROPE

Event date :

5 September 2016 through 9 September 2016

Audience :

International

Journal title :

IEEE International Symposium on Electromagnetic Compatibility

ISSN :

1077-4076

Publisher :

Institute of Electrical and Electronics Engineers Inc.

Volume :

2016-November

Pages :

382-387

Peer reviewed :

Peer reviewed

Commentary :

9781509014163

Available on ORBi :

since 07 June 2019

Statistics

Number of views

43 (3 by ULiège)

Number of downloads

3 (3 by ULiège)

More statistics

Scopus citations^®

Scopus citations^®
without self-citations

OpenCitations

Bibliography

J. M. Redout and M. Steyaert, EMC of Analog Integrated Circuits, Springer, 2010.
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.
G. Matig-a, M. R. Yuce, and J. M. Redoute, An Integrated LVDS Transmitter in 018um CMOS Technology with High Immunity to EMI, IEEE Transactions Electromagnetic Compatibility, pp 1-7, Oct. 2014.
G. Matig-a, M. R. Yuce, and J. M. Redoute, An Integrated LVDS Transmitter-Receiver System with Increased Self-Immunity to EMI in 0. 18um CMOS, IEEE Transactions Electromagnetic Compatibility, pp 1-10, Dect. 2015.
High-Definition Multimedia Interface (HDMI) specification, Specification version 1. 4a, http: //www. hdmi. org.
Interfacing between LVPECL, VML, CML, and LVDS levels, Application Report SLLA120, Texas Instruments, Dec. 2002.
IEEE standard for low-voltage differential signals (LVDS) for scalable coherent interface (SCI), 1596. 3 SCI-LVDS standard, IEEE Std 1596. 3-1996, 1996.
A. Boni, A. Pierazzi, D. Vecchi, LVDS I/O Interface for Gb/s-per-Pin Operation in 0. 35-um CMOS, IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr. 2001.
A. Tajalli, Y. Leblebici, A Slew Controlled LVDS Output Driver Circuit in 0. 18um CMOS Technology, IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 538-548, Feb. 2009.
G. Matig- A and H. Y. Huang, Preemphasis and Equalization Based LVDS Transmitter and Receiver, Springer Journal on Analog Integrated Circuits and Signal Processing, vol. 75, no. 1, pp. 109-123, Apr. 2013.
N. Gupta, P. Bala, V. K. Singh, "Area and Power Efficient 3. 4Gbps/Channel HDMI Transmitter with Single-Ended Structure", VLSI Design and 2013 12th International Conference on Embeded Systems (VLSID), Pune, India, Jan 2013.
B. Song, K. Kim, J. Lee, J. Burm, A 0. 18um CMOS 10-Gb/p Dual-Mode 10-PAM Serial Link Transceiver, IEEE Trans. Circuits Syst. I. Reg. Papers, vol. 60, no. 2, pp. 457-468, Feb 2013.
H. Cheng, F. A. Musa, and A. C. Carusone, A 32/16-Gb/s dual-mode pulsewidth modulation re-emphasis (PWM-PE) transmitter with 30-dB loss compensation using a high-speed CML design methodology, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 8, pp. 1794-1806, Aug. 2009.
Y. H. Song, R. Bai, K. Hu, H. W. Yang, P. Y. Chiang, and S. Palermo, A 0. 47-0. 66 pJ/bit, 4. 8-8 Gb/s I/O Transceiver in 65 nm CMOS, IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 1276-1289, May 2013.
S. K. Lee, B. Kim, H. J. Park, and J. Y. Sim, A QDR-Based 6-GB/s Parallel Trasnceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, pp. 91-95, Feb. 2013.
Measurement of E/M Immunity 150kHz to 1GHz Part 4: Direct Power Injection Method, IEC62132-4, Ed. 1: ICs, 2004.