Modeling and design of an EMI-immune source-buffered miller OpAmp in 0.18 μm CMOS technology

Boyapati, S.; Redouté, Jean-Michel; Baghini, M. S.

doi:10.1109/EMCEurope.2017.8094633

Request a copy

Paper published in a book (Scientific congresses and symposiums)

Modeling and design of an EMI-immune source-buffered miller OpAmp in 0.18 μm CMOS technology

Boyapati, S.; Redouté, Jean-Michel; Baghini, M. S.

2017 • In 2017 International Symposium on Electromagnetic Compatibility - EMC EUROPE 2017, EMC Europe 2017

Peer reviewed

Permalink
https://hdl.handle.net/2268/236418

DOI
10.1109/EMCEurope.2017.8094633

Files (1)Send to Details Statistics Bibliography Similar publications

Files

Full Text

2017 - Modeling and design of an EMI-immune source-buffered miller OpAmp in 0.18 μm CMOS technology.pdf

Publisher postprint (394.87 kB)

Request a copy

All documents in ORBi are protected by a user license.

Send to

RIS BibTex APA Chicago Permalink X Linkedin

Details

Keywords :

Electromagnetic interference immunity; EMI modeling; Operational amplifiers with high EMI immunity; Source-buffered; CMOS integrated circuits; Electromagnetic compatibility; Electromagnetic pulse; Electromagnetic wave interference; Integrated circuit design; Signal interference; Body effect; Channel length modulation; CMOS processs; CMOS technology; Miller operational amplifiers; Offset voltage; Operating condition; Operational amplifiers

Abstract :

[en] This paper presents the modeling and design of a source-buffered Miller operational amplifier structure that is highly immune to electromagnetic interference (EMI). The source-buffered Miller operational amplifier is designed and fabricated in the 0.18 μm mixed-mode CMOS process and modeled mathematically including the body effect and channel length modulation. Measurement results show that the maximum EMI-induced input offset voltage for the source-buffered Miller operational amplifier is 22 mV at 1 GHz, when a 900 mVpp EMI signal is applied at its input. In contrast, the standard Miller operational amplifier generates an input offset voltage of 215 mV under the same operating conditions. © 2017 IEEE.

Disciplines :

Electrical & electronics engineering

Author, co-author :

Boyapati, S.; IITB-Monash Research Academy, Indian Institute of Technology, Bombay, India

Redouté, Jean-Michel ; Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes microélectroniques intégrés

Baghini, M. S.; Dept. of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India

Language :

English

Title :

Modeling and design of an EMI-immune source-buffered miller OpAmp in 0.18 μm CMOS technology

Publication date :

2017

Event name :

2017 International Symposium on Electromagnetic Compatibility - EMC EUROPE, EMC Europe 2017

Event date :

4 September 2017 through 8 September 2017

Audience :

International

Main work title :

2017 International Symposium on Electromagnetic Compatibility - EMC EUROPE 2017, EMC Europe 2017

Publisher :

Institute of Electrical and Electronics Engineers Inc.

Peer reviewed :

Peer reviewed

Commentary :

9781538606896

Available on ORBi :

since 07 June 2019

Statistics

Number of views

37 (3 by ULiège)

Number of downloads

3 (3 by ULiège)

More statistics

Scopus citations^®

Scopus citations^®
without self-citations

OpenCitations

Bibliography

M.T. Abuelma'atti, "Analysis of the effect of radio frequency interference on the DC performance of CMOS operational ampliers," in Analog integrated circuits and signal processing (Springer, The Netherlands, 2005), vol. 45, pp. 123-130.
A. Richelli, L. Colalongo, ZS. M. Kovacavanja, "Increasing the Immunity to Electromagnetic Interferences of CMOS Operational Amplifiers," IEEE Trans. Reliab., Vol. 52, no. 3, pp. 349-353, Sept. 2003.
W. Sansen, "Distortion in elementary transistor circuits," IEEE Trans. Circuits Syst. II, Vol. 46, pp. 315-325, Mar. 1999.
P. Wambacq, and W. Sansen, "Distortion analysis of analog integrated Circuits". Norwell, MA: Kluwer, 1998.
F. Fiori, "A new nonlinear model of EMI-induced distortion phenomena in feedback CMOS operational amplifiers," IEEE Trans. Electromagn. Compat., Vol. 44, no. 4, pp. 495-502, Nov. 2002.
F. Fiori, "Design of an operational amplifier input stage immune to EMI," IEEE Tran. Electromagn. Compat., Vol. 49, no. 4, pp. 834-839, Nov. 2007.
J-M. Redouté, and M. Steyaert, "A CMOS source-buffered differential input stage with high EMI supression," in Proc. Eur. Solid-State Circuits Conference., Edinburgh, U.K., Sep. 2008, pp. 318-321.
A. Richelli, "CMOS OpAmp resisting to large electromagnetic interferences," IEEE Trans. Electromagn. Compat., Vol. 52, no. 4, pp. 1062-1065, Nov. 2010.
F. Fiori, "Operational amplier input stage robust to EMI," Electron. Lett., Vol. 37, no. 15, pp. 930-931, Jul. 2001.
S. Boyapati, J-M. Redouté, and M. Shojaei Baghini "Modeling and Design of EMI Immune OpAmp's in 0.18μm CMOS Technology," IEEE Trans. Electromagn. Compat., Vol. 58, no. 5, pp. 1609-1616, June. 2016.
B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, 2001.