Reference : EMI-resistant CMOS differential input stages
Scientific journals : Article
Engineering, computing & technology : Electrical & electronics engineering
http://hdl.handle.net/2268/229083
EMI-resistant CMOS differential input stages
English
Redouté, Jean-Michel mailto [Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes microélectroniques intégrés >]
Steyaert, M. S. J. [Department of Electrotechnical Engineering (ESAT), MICAS, Katholieke Universiteit Leuven, 3001 Leuven, Belgium]
2010
IEEE Transactions on Circuits and Systems I: Regular Papers
57
2
323-331
Yes (verified by ORBi)
International
1549-8328
[en] CMOS analog integrated circuits ; Differential pairs ; Electromagnetic compatibility ; Electromagnetic interference ; Input terminals ; Offset voltage ; Test chips ; Analog circuits ; Electromagnetic pulse ; Electromagnetic wave interference ; Electromagnetism ; Integrated circuits ; Linear integrated circuits ; Signal interference ; Topology ; CMOS integrated circuits
[en] This paper studies and compares the performances of CMOS differential input stages with a high degree of immunity against electromagnetic interferences (EMIs) and introduces a source-buffered differential pair which is very resistant to EMI coupled at its inputs. The EMI behavior of this source-buffered differential-pair topology has been evaluated with a test chip: When injecting an EMI signal of 750 mV rms at the input terminals, the measured maximal EMI-induced input offset voltage corresponds to 116 mV for the source-buffered topology compared with 610 mV for the classic differential pair, which constitutes a major improvement. © 2006 IEEE.
IWT, OIST PC, Okinawa Institute of Science and Technology Promotion Corporation; NCSR, National Council for Scientific Research; IEEE, IEEE Foundation; UCLA, University of California, Los Angeles; Department of Electrical Engineering, Chulalongkorn University; KU Leuven
http://hdl.handle.net/2268/229083
10.1109/TCSI.2009.2023836

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