EMI-resistant CMOS differential input stages

CMOS analog integrated circuits; Differential pairs; Electromagnetic compatibility; Electromagnetic interference; Input terminals; Offset voltage; Test chips; Analog circuits; Electromagnetic pulse; Electromagnetic wave interference; Electromagnetism; Integrated circuits; Linear integrated circuits; Signal interference; Topology; CMOS integrated circuits

Abstract :

[en] This paper studies and compares the performances of CMOS differential input stages with a high degree of immunity against electromagnetic interferences (EMIs) and introduces a source-buffered differential pair which is very resistant to EMI coupled at its inputs. The EMI behavior of this source-buffered differential-pair topology has been evaluated with a test chip: When injecting an EMI signal of 750 mV rms at the input terminals, the measured maximal EMI-induced input offset voltage corresponds to 116 mV for the source-buffered topology compared with 610 mV for the classic differential pair, which constitutes a major improvement. © 2006 IEEE.

Disciplines :

Electrical & electronics engineering

Author, co-author :

Redouté, Jean-Michel ; Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes microélectroniques intégrés

Steyaert, M. S. J.; Department of Electrotechnical Engineering (ESAT), MICAS, Katholieke Universiteit Leuven, 3001 Leuven, Belgium

Language :

English

Title :

EMI-resistant CMOS differential input stages

Publication date :

2010

Journal title :

IEEE Transactions on Circuits and Systems I: Regular Papers

ISSN :

1549-8328

eISSN :

1558-0806

Publisher :

Institute of Electrical and Electronics Engineers, United States

Volume :

Issue :

Pages :

323-331

Peer reviewed :

Peer Reviewed verified by ORBi

Available on ORBi :

since 04 November 2018

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Bibliography

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