Reference : An Integrated LVDS Transmitter-Receiver System with Increased Self-Immunity to EMI in...
Scientific journals : Article
Engineering, computing & technology : Electrical & electronics engineering
http://hdl.handle.net/2268/227768
An Integrated LVDS Transmitter-Receiver System with Increased Self-Immunity to EMI in 0.18-μm CMOS
English
Matig-A, G. A. [Department of Electrical and Computer Systems Engineering, Monash University, Melbourne, VIC 3800, Australia]
Yuce, M. R. [Department of Electrical and Computer Systems Engineering, Monash University, Melbourne, VIC 3800, Australia]
Redouté, Jean-Michel mailto [Université de Liège - ULiège > Dép. d'électric., électron. et informat. (Inst.Montefiore) > Systèmes microélectroniques intégrés >]
2016
IEEE Transactions on Electromagnetic Compatibility
Institute of Electrical and Electronics Engineers Inc.
58
1
231-240
Yes (verified by ORBi)
International
00189375
[en] Bit error rate ; CMOS integrated circuits ; Electromagnetic pulse ; Integrated circuit design ; Transmitters ; Common Mode Range ; Communication bus ; Low voltage differential signaling ; LVDS transmitters ; Receiver circuits ; Receiver system ; Supply voltages ; Transverse electromagnetic cell (TEM) ; Signal receivers
[en] This paper presents the design of an integrated low-voltage differential signaling (LVDS) transmitter-receiver system with a superior immunity to electromagnetic interference (EMI). The effects of injected RF interference on the differential communication bus between the proposed and typical LVDS transmitter and receiver front-ends are presented and explained mathematically. The design of a proposed wide input common-mode range LVDS receiver with an increased noise margin is discussed in detail. Transverse electromagnetic (TEM) cell measurements confirm that the proposed LVDS transmitter-receiver yields a worst-case bit error rate (BER) of 0.1 for an injected 30-dBm EMI signal at 840 MHz, while the typical transmitter-receiver pair fails with a BER of 0.5 for EMI levels as low as 23 dBm at frequencies ranging from 650 to 800 MHz, 820 to 860 MHz, and at 560 MHz. The discussed LVDS transmitter-receiver circuits were designed using the UMC 0.18-μm CMOS process with a supply voltage of 1.8 V. © 1964-2012 IEEE.
http://hdl.handle.net/2268/227768
10.1109/TEMC.2015.2505005

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