Study of interface trap density in a GeSn MOS structure by numerical simulation of the electrical characteristics

The semiconducting alloy germanium tin (GeSn) is expected to play an important role in the development of high mobility channel materials for next generation CMOS and optoelectronic devices. The two most interesting features of this material, which is compatible with mainstream Si technology, are its tunable direct band-gap and the possibility to induce strain due to the lattice mismatch with Ge and Si, thereby increasing the holes and electrons mobilities. It has been shown that the interface trap density can be under- or overestimated in Ge-channel MOSFETs when applying conventional measurement techniques such as the conductance method. As this effect is common in low band-gap materials, we expect that it also occurs for GeSn. Following our previous work on metal/GeSn/Ge structures, we have therefore applied our home-built numerical simulation software to a metal/oxide/GeSn MOS structure in order to investigate the result of the presence of such interface states. We discuss possible effects of the interface trap density, interface trap energy and temperature on the electrical characteristics. Successive simulations of both the steady-state and ac small-signal regimes give access to measurable quantities such as the admittance spectrum and the C-V curves. A physical interpretation can be attributed to their variations and an overall comparison can be made with results obtained from equivalent electrical circuit analysis.