Baert, B. (2016). Impact of electron trap states on the transport properties of GeSn semiconducting heterostructures assessed by electrical characterizations [Doctoral thesis, ULiège - Université de Liège]. ORBi-University of Liège. https://orbi.uliege.be/handle/2268/201505 |
Baert, B., Gupta, S., Gencarelli, F., Loo, R., Simoen, E., & Nguyen, N. D. (August 2015). Electrical characterization of p-GeSn/n-Ge diodes with interface traps under dc and ac regimes. Solid-State Electronics, 110, 65-70. doi:10.1016/j.sse.2015.01.007 |
Baert, B., Cerica, D., Schmeits, M., & Nguyen, N. D. (13 November 2014). Electrical modelling of interface traps in GeSn MOS structures [Paper presentation]. JSPS International Core-to-Core Program Workshop on Atomically Controlled Processing for Ultra-large Scale Integration, Leuven, Belgium. |
Baert, B., Gupta, S., Gencarelli, F., Loo, R., Simoen, E., & Nguyen, N. D. (03 June 2014). Electrical characterization of pGeSn/nGe diodes [Paper presentation]. 7th International Silicon-Germanium Technology and Device Meeting (2014 ISTDM), Singapore. doi:10.1109/ISTDM.2014.6874640 |
Baert, B., & Nguyen, N. D. (June 2012). Numerical Simulation of the Electrical Characteristics of GeSn/Ge Semiconducting Heterostructures [Poster presentation]. "Jaszowiec" International School and Conference on the Physics of Semiconductors. |
Baert, B., Nakatsuka, O., Zaima, S., & Nguyen, N. D. (2012). Impedance spectroscopy of GeSn/Ge heterostructures by a numerical method. In 222nd ECS Meeting, 2012. ECS. |